GENERAL DESCRIPTION
ThePRN256M16V00HG8GNF-125isa high performancedynamic random-access 4Gb device. These components areorganized in a x16 configuration, and utilize 8 bankarchitecture with a synchronous DDR3 interface.These DDR3 SDRAM components use double data ratearchitecture to achieve high speed operation.
Features
Vdd = VddQ =1.5V +0.075V 1.5Vcenter-terminated push / pull I/O Differentialbidirectional data strobe 8n-bitprefetch architecture Differentialclock inputs (CK, CK#) 8internal banks Nominal anddynamic on-die termination (ODT) For data,strobe, and mask signals ProgrammableCAS READ latency (CL) Posted CASadditive latency (AL) ProgrammableCAS WRITE latency (CWL) based on tCKFixed burstlength (BL) of 8 and burst chop (BC) of 4 (via the moderegister set [MRS] Selectable BC4or BL8 on-the-fly (OTF) Self refreshmode Tcof 0C to +95C 64ms 8192cycle refresh at 0C to 85C 32ms 8192cycle refresh at +85C to +95C Self refreshtemperature (SRT) Writeleveling Multipurposesregister Output drivercalibration