GENERAL DESCRIPTION
ThePRN256M8V89CG8G the PRN128M16V89CG8GNF-15Eishigh performance dynamicrandom-access 2Gb device respectively. These components areorganized in a x8 configuration, and utilize 8 bankarchitecture with a synchronous DDR3 interface.These DDR3 SDRAM components use double data ratearchitecture to achieve high speed operation.
DDR3 SDRAM
PRN256M8V89CG8G9CG8GNF-15EPRN 256M8 – 32Meg x 8 x 8 Banks PRN 128M8 –16Meg x 16 x 8 Banks
Features
Vdd = VddQ =1.5V +0.075V
1.5Vcenter-terminated push / pull I/O
Differentialbidirectional data strobe
8n-bit prefetcharchitecture
Differentialclock inputs (CK, CK#)
8 internalbanks
Nominal anddynamic on-die termination (ODT) For data, strobe, and masksignals
Programmable CASREAD latency (CL) Posted CAS additive latency(AL)
Programmable CASWRITE latency (CWL) based on tCK
Fixed burstlength (BL) of 8 and burst chop (BC) of 4 (via the mode register set[MRS]
Selectable BC4or BL8 on-the-fly (OTF)
Self refreshmode
Tc of 0C to+95C
64ms 8192 cyclerefresh at 0C to 85C
32ms 8192 cyclerefresh at +85C to +95C
Self refreshtemperature (SRT)
Writeleveling
Multipurposesregister
Output drivercalibration
